1. Technical Field
The present invention is directed to data processing systems. More specifically, the present invention is directed to a method, apparatus, and computer program product for synchronizing the triggering of multiple hardware trace facilities using an existing system bus.
2. Description of Related Art
Making tradeoffs in the design of commercial server systems has never been simple. For large commercial systems, it may take years to grow the initial system architecture draft into the system that is ultimately shipped to the customer. During the design process, hardware technology improves, software technology evolves, and customer workloads mutate. Decisions need to be constantly evaluated and reevaluated. Solid decisions need solid base data. Servers in general and commercial servers in particular place a large demand on system and operator resources, so the opportunities to collect characterization data from them are limited.
Much of performance analysis is based on hardware-collected traces. Typically, traces provide data used to simulate system performance, to make hardware design tradeoffs, to tune software, and to characterize workloads. Hardware traces are almost operating system, application, and workload independent. This attribute makes these traces especially well suited for characterizing the On-Demand and Virtual-Server-Hosting environments now supported on the new servers.
A symmetric multiprocessing (SMP) data processing server has multiple processors with multiple cores that are symmetric such that each processor has the same processing speed and latency. An SMP system could have multiple operating systems running on different processors, which are a logically partitioned system, or multiple operating systems running on the same processors one at a time, which is a virtual server hosting environment. Operating systems divide the work into tasks that are distributed evenly among the various cores by dispatching one or more software threads of work to each processor at a time.
A single-thread (ST) data processing system includes multiple cores that can execute only one thread at a time.
A simultaneous multi-threading (SMT) data processing system includes multiple cores that can each concurrently execute more than one thread at a time per processor. An SMT system has the ability to favor one thread over another when both threads are running on the same processor.
As computer systems migrate towards the use of sophisticated multi-stage pipelines and large SMP with SMT based systems, the ability to debug, analyze, and verify the actual hardware becomes increasingly more difficult, during development, test, and during normal operations. A hardware trace facility may be used which captures various hardware signatures within a processor as trace data for analysis. This trace data may be collected from events occurring on processor cores, busses (also called the fabric), caches, or other processing units included within the processor. The purpose of the hardware trace facility is to collect hardware traces from a trace source within the processor and then store the traces in a predefined memory location.
As used herein, the term “processor” means a central processing unit (CPU) on a single chip, e.g. a chip formed using a single piece of silicon. A processor includes one or more processor cores and other processing units such as a memory controller, cache controller, and the system memory that is coupled to the memory controller.
This captured trace data may be recorded in the hardware trace facility and/or within another memory. The term “in-memory tracing” means storing the trace data in part of the system memory that is included in the processor that is being traced.
There is need to have a global triggering mechanism that can be used to synchronize simultaneous collection of different traces. Simultaneous collection of different traces is sometimes important in tuning software, and/or characterizing workloads. For example, the developers are faced with the vexing problem of determining the origin of some rather long lock acquisition sequences in a multiprocessor system.
Moreover there is a need to have more than one trace facility simultaneously collecting different parts from the bus trace to reduce the chance of losing trace record because one trace facility alone can not handle the bus trace bandwidth. Therefore, a global triggering mechanism is needed that can control all trace facility with the same triggers.
In the prior art, the multiple hardware trace facilities did not receive triggers utilizing an existing, standard bus and its standard bus protocols. A special purpose trigger bus existed that coupled existing hardware trace facilities together. This special purpose bus was dedicated to sending only triggers to the hardware trace facilities using a special trace bus protocol. Triggers were transmitted to the hardware trace facilities using only the special purpose dedicated bus.
In the prior art, only one hardware trace facility could be assigned to be the master. Thus, only the one hardware trace facility could send out triggers. All other hardware trace facilities had to be configured to receive triggers from this master.
Therefore, a need exists for a method, apparatus, and computer program product for synchronizing the triggering of multiple hardware trace facilities using an existing system bus.